1. Field of the Invention
The present invention relates to a DMA transfer controller capable of a time control of a DMA transfer.
2. Description of the Related Art
In recent years, with the progress of the multi-media of devices, audio data or a moving image (AV) has been ordinarily encoded or decoded on a processor. Generally, when the AV is decoded, a prescribed amount of process needs to be completed within a prescribed time. Namely, a real time process is necessary. Further, in the interactive communication of the audio data and the moving image, an encoding process also needs to be performed in a real time.
When a plurality of processes including such real time processes are performed on a single processor, a mechanism for ensuring the real time characteristics of the processes is necessary. As one of methods for realizing this mechanism, there is a system that the time division of resources of the processor is carried out and the contents of the processes are changed for each prescribed time. This system is generally equivalent to a system that a plurality of virtual logical processors performs respectively different processes in parallel. This system is called a virtual multi-processing (VMP), hereinafter.
In the AV process, a large quantity of data needs to be transferred via an inner data bus between an input and output device, a buffer memory (a temporarily storing memory of data) and a work memory (a data processing memory). Ordinarily, the resources of the processor are not preferably consumed for the transfer of data. Thus, the data is ordinarily transferred by using a DMA (direct memory access) controller.
With the recent increase of the throughput of information in a system LSI, a quantity of data transferred in an inner bus of the LSI is also steadily increasing. To efficiently transfer the data, a high functional DMA controller is likewise required. Various kinds of DMA controllers have been proposed. For instance, a DMA controller in which priority is given to a plurality of DMA transfers in order to improve a transfer efficiency (see Patent Document 1: JP-A-9-223102) or a DMA controller in which a plurality of DMA transfers are reserved and performed (see Patent Document 2: JP-A-2002-41445) are devised.
FIG. 2 is a block diagram showing a structural example of a system with which a usual DMA controller is loaded. In FIG. 2, a microprocessor unit (MPU) 1 includes a processor 11, an inner DMA controller 12, an external DMA bus interface 13 and inner memories 14 and 15 and 16. Members 11 to 16 are respectively connected to a processor inner bus and an inner DMA bus mounted on the MPU. Further, MPU1, an external DMA controller 2, a peripheral circuit 3, an external memory 4 and a peripheral circuit 5 are connected to an external DMA bus of the MPU.
Now, a case that compressed audio data is read from a storage device (for instance, a semiconductor memory card) by using the system shown in FIG. 2, decoded and then the decoded data is outputted from an audio interface circuit is considered. In this case, the peripheral circuit 3 serves as an interface circuit to the semiconductor memory card and the peripheral circuit 5 serves as the audio interface circuit.
To uninterruptedly reproduce the audio data, a program (refer it to as a program C) for performing an audio data decoding process needs real time characteristics. Further, two programs A and B having non-real time characteristics are performed in parallel with the audio decoding program C. The operations of the processor 11 and the inner DMA controller 12 are shown in a timing chart in FIG. 3.
The flow of the data and processes in the audio decoding process are described below.
(Process 1) The external DMA controller 2 always transfers the compressed audio data from the peripheral circuit 3 to the external memory 4. This process does not need to be paid attention to when the operation of the inner DMA controller 12 is considered.
(Process 2) The inner DMA controller 12 transfers the results of a past decoding process to the peripheral circuit 5 from the inner memory 14. This DMA transfer is started by the program C.
(Process 3) When the DMA transfer of the process 2 is completed, the inner DMA controller 12 informs the processor 11 of an interrupt. Thus, the program C starts a next DMA transfer and the inner DMA controller 12 transfers new compressed data to the inner memory 14 from the external memory 4 subsequently to the process 2. In the processes 2 and 3, the inner memory 14 is used as a buffer memory.
(Process 4) In the processor 11, a decoding process of data held in the inner memory 15 is performed in parallel with the above-described processes 2 and 3. In this process, the inner memory 15 is used as a work memory.
The processes 2 to 4 are repeated for each prescribed unit time for processing and the uses of the inner memories 14 and 15 are alternately changed for each unit time. That is, the inner memory 14 is used as the buffer memory for a prescribed time and is used as the work memory for another time. This may be applied to the inner memory 15.
In this system, to assure the real time characteristics of the program C, the programs A, B and C are performed in time division as shown in FIG. 3. This state may be considered to be a state that the programs A, B, and C are performed by respectively individual virtual logical processors. In the case of the audio data decoding process, the “unit time for processing” shown in FIG. 3 is ordinarily determined from an encoding system, the output data rate (a quantity of output data per unit time) of the peripheral circuit, the capacity of a buffer, etc.
Further, in this system, since the virtual multi-processing is introduced, when the programs (A, B, C) are respectively developed, the contents of processes or the executing time of other programs do not need to be taken into consideration. On the assumption that the prescribed resources of the processor are respectively assured for the programs, the development of the programs can be independently advanced. Namely, the virtual multi-processing not only can assure a real time process, but also has an advantage that the programs can be easily developed. Further, because of the same reasons, the programs A and B can be easily transported to another system having different unit time for processing.
Now, to show the problems of this system, a case that a specific program occupies a DMA bus for a long time is considered. In an operational example shown in a timing chart of FIG. 4, the program B performs the DMA transfer having a large quantity of transfer and occupies the DMA bus for a long time. When this DMA transfer is completed and the DMA bus is opened, the program C performs the DMA transfer to the peripheral circuit 5 from the inner memory 15. After the transfer is completed, the program C informs the processor 11 of an interrupt.
However, in the timing chart shown in FIG. 4, when the processor 11 is informed of the interrupt, the process of the program C is already completed, so that a next DMA transfer cannot be subsequently activated. When the program C starts the data process of the inner memory 15, since data to be processed has not been transferred, a real time process fails.
Some methods for avoiding such a situation may be considered. One of the methods is that a plurality of DMA transfers are subscribed and performed. That is, as shown in a timing chart of FIG. 5, a DMA transfer request for the inner memory 15 may be previously subscribed from the external memory. After the DMA transfer is completed from the inner memory 15 to the peripheral circuit 5, the subscribed DMA transfer may be automatically performed. Specifically, this process can be realized by using the DMA controller disclosed in the Patent Document 2.
However, even when the plurality of DMA transfers can be subscribed and performed, the real time characteristics of the program C may not be possibly assured. For instance, in an operational example shown in a timing chart of FIG. 6, since the DMA transfer time of the program B is long, the completion of the DMA transfer is not finished until the process of the inner memory 15 is started. Thus, the real time process fails.
Finally, to assure a DMA bus access for a prescribed time for the DMA transfer of the program C, there is no other assured method than a method that a restriction is applied to the start timing and transfer time (or the number of transferred words) of the DMA transfers activated by the programs A and B. As apparent from the above-described consideration, when a real time process is carried out, only the time division (an introduction of VMP) of the resources of the processor is insufficient and a time control (scheduling) of the DMA transfer needs to be considered together.
As described above, in the development of the programs A and B, when these programs perform a DMA transfer request, the real time process of the program C needs to be considered so as not to fail. However, in the development of the programs A, B and C, a dependent relation is thus generated between them, so that the programs cannot be independently progressively developed. In such a way, the advantage of the VMP that the programs are easily developed is seriously damaged due to the scheduling of the DMA transfers.
Further, in the AV encoding/decoding process, since time required for the process is different depending on the encoding system or the input and output data rate, the unit time for processing may have various values. Thus, in all cases, it is necessary to assure that the system does not fail.
Further, when a plurality of real time processes are congested, the development of the system and the number of inspecting processes are enormously increased. In addition thereto, the scheduling itself having no failure of the system may be sometimes hardly performed.